The present invention relates to a semiconductor storage device and, particularly, to a semiconductor storage device in which power supplies of a memory array and a peripheral circuit are separated.
Reducing a standby current for a SRAM (Static Random Access Memory) has so far been pursued. In a certain SRAM, a separate supply voltages are supplied to memory cells in a memory array and to a peripheral circuit and it is contrived to reduce a standby current by shutting off the supply of the supply voltage to the peripheral circuit during standby (Patent Document 1).
Also, a scheme is used that reduces operating power, while maintaining data retention properties by decreasing the supply voltage to a peripheral circuit, while keeping the supply voltage to the memory array high during operation.
In a case where a memory has two power supplies: a power supply for memory cells in a memory array and a supply voltage for a peripheral circuit, a rule of power-on sequence is generally established.
For example, a rule of power-on sequence specifies that the supply voltage for a peripheral circuit must be turned on first before turning on the power supply for memory cells in a memory array.
If such rule is not observed, there is a possibility of trouble occurring, such as a through-current flowing from one power supply to another power supply according to turn-on order, malfunction, and failure.
Therefore, such a power-on sequence is often prescribed in SRAM specifications.